The present invention relates to a semiconductor device and a method for manufacturing the same, and more particularly, to a semiconductor device which has improved performance characteristics and a method for manufacturing the same.
It is well known that the continued demands for higher speed operations and for higher integration of a semiconductor device have continued to rapidly drive the development of various semiconductor technologies. As a result these demands requirements for more refined patterns, i.e., higher precision and higher accuracy in the underlying circuit patterns have also increased. These requirements are applied not only to patterns that are formed in device regions but also to an isolation structure that occupies a relatively large area.
The isolation structure is usually formed using an STI (shallow trench isolation) process. This is because the isolation structure formed using the STI process enjoys the benefits of having a small width and excellent isolation characteristics. For this reason, in most semiconductor devices, isolation structures are formed using the STI process.
As the integration degree of a semiconductor device is increased, the width of a trench necessarily decreases, however the need remains to assure that the relative depth of the these trench are increased. In this regard, a problem arises when filling the trench due to this increased aspect ratio demand in the trenches.
Under these situations, an HARP (high aspect ratio process) or a PDL (pulsed deposition layer) is adopted to address this problem caused when filling a trench. However, since the HARP or PDL employs a conformal deposition method, undesirable limitations remain in properly filling a trench. Hence, an isolation structure is currently formed using a single layer comprising an HDP (high density plasma) layer or an SOD (spin-on dielectric) layer or using the stack of a lower SOD layer having excellent gap-fill capability and an upper HDP layer having high density.
Nevertheless, although not shown in a drawing, in the case of the single layer comprising the HDP layer, as the width of a trench gradually decreases with the high integration of a semiconductor device, adequate gap-filling becomes impossible. Accordingly, it is anticipated that an isolation structure comprising the single layer of the HDP layer will be difficult to provide when applied to a next-generation of highly integrated semiconductor devices.
Also, in the case of the single layer comprising the SOD layer, contraction can occur due to a moat phenomenon and as a result the resultant SOD layer can be deformed. That is, when subsequently forming recess gates, the space between the gates is reduced and the margin of a recessing process decreases so that the process for forming landing plug contacts can fail. Accordingly, manufacturing non-deformed isolation structures that comprise single SOD layers is difficult to achieve.
Further, in the case of manufacturing the stack isolation structures that comprise the SOD layer and the HDP layer, cracks and punch-through are likely to occur due to the deformed resultant SOD layer and due to the differences in stress between the SOD layer and the HDP layer. Accordingly, making a non-deformed isolation structure comprising the stack of the SOD layer and the HDP layer is also difficult to achieve.
Thus, novel measures for solving the problems caused when filling a trench having a substantial aspect ratio are keenly demanded in the art.